Power Management; Parameters Defined Separately For All Port Functions; Base Address Registers For Function <N; Base And Limit Registers For Root Port Func <N - Altera Cyclone V User Manual

Chapter 3: Parameter Settings
Port Functions
Table 3–5. Slot Capabilities
Parameter
Slot power limit
0–255
Slot number
0-8191

Power Management

Table 3–6
Table 3–6. Power Management Parameters
Parameter
Endpoint L0s
< 64 ns – > No limit
acceptable latency
Endpoint L1
< 1 µs to > No limit
acceptable latency

Parameters Defined Separately for All Port Functions

The Port Functions tab allows you to specify parameter settings for up to eight
functions. Each function has separate settings for the following parameters:
■ Base Address Registers for Function <n>
■ Base and Limit Registers for Root Port Func <n>
■ Device ID Registers for Function <n>
■ PCI Express/PCI Capabilities for Func <n>
November 2011 Altera Corporation
0x094
Value
In combination with the Slot power scale value, specifies the upper limit in watts on
power supplied by the slot. Refer to Section 7.8.9 of the
for more information.
Revision 2.1
Specifies the slot number.
describes the Power Management parameters.
Value
This design parameter specifies the maximum acceptable latency that the
device can tolerate to exit the L0s state for any links between the device and
the root complex. It sets the read-only value of the Endpoint L0s acceptable
latency field of the Device Capabilities register (0x084).
The Cyclone V Hard IP for PCI Express does not support the L0s or L1
states. However, in a switched system there may be links connected to
switches that have L0s and L1 enabled. This parameter is set to allow
system configuration software to read the acceptable latencies for all
devices in the system and the exit latencies for each link to determine which
links can enable Active State Power Management (ASPM). This setting is
disabled for Root Ports.
The default value of this parameter is 64 ns. This is the safest setting for
most designs.
This value indicates the acceptable latency that an Endpoint can withstand
in the transition from the L1 to L0 state. It is an indirect measure of the
Endpoint's internal buffering. It sets the read-only value of the Endpoint L1
acceptable latency field of the Device Capabilities register.
The Cyclone V Hard IP for PCI Express does not support the L0s or L1
states. However, in a switched system there may be links connected to
switches that have L0s and L1 enabled. This parameter is set to allow
system configuration software to read the acceptable latencies for all
devices in the system and the exit latencies for each link to determine which
links can enable Active State Power Management (ASPM). This setting is
disabled for Root Ports.
The default value of this parameter is 1 .µs. This is the safest setting for
most designs.
Description
PCI Express Base Specification
Description
Cyclone V Hard IP for PCI Express
3–7
User Guide