Pipe Interface Signals - Altera Cyclone V User Manual

Chapter 5: IP Core Interfaces
Physical Layer Interface Signals
Figure 5–20
Figure 5–20. Channel Placement for ×1 and ×4 Variants
Transceiver Bank
x1
Channel 5
Channel 4
Channel 3
Channel 2 - Data
Channel 1 - CMU PLL
Channel 0 -
LCD
Data
LCD = Local Clock Divider

PIPE Interface Signals

The PIPE signals are available so that you can simulate using either the one-bit or the
PIPE interface. Simulation is much faster using the PIPE interface. You can use the 8-
bit PIPE interface for simulation even though your actual design includes the serial
interface to the internal transceivers. However, it is not possible to use the Hard IP
PIPE interface in an actual device.
for a standard 16-bit SDR or 8-bit SDR interface. In
lane number 0 also exist for lanes 1-7. In Qsys, the signals that are part of the PIPE
interface have the prefix, hip_pipe. The signals which are included to simulate the PIPE
interface have the prefix, hip_pipe_sim_pipe.
Table 5–22. PIPE Interface Signals (Part 1 of 3)
Signal
txdata0[15:0]
(1)
txdatak0[1:0]
(1)
txdetectrx0
(1)
txelecidle
November 2011 Altera Corporation
shows the channel placement for ×1 and ×4 variants.
Other
Protocols
PCI Express Lane 0
Table 5–22
I/O
O Transmit data <n>. This bus transmits data on lane <n>.
Transmit data control <n>. This signal serves as the control bit for
O
txdata<n>.
Transmit detect receive <n>. This signal tells the PHY layer to start a
O
receive detection operation or to begin loopback.
Transmit electrical idle <n>. This signal forces the TX output to electrical
O
idle.
Transceiver Bank
x4
Channel 5
Protocols
Channel 4 - CMU PLL
Channel 3 - Data
Channel 2 - Data
Channel 1
CCD
Data
Channel 0 - Data
CCD = Central Clock Divider
describes the PIPE interface signals used
Table 5–22, signals that include
Description
Cyclone V Hard IP for PCI Express
5–33
Other
PCI Express Lane 3
PCI Express Lane 2
PCI Express Lane 1
PCI Express Lane 0
User Guide