Qsys Design Flow; Customizing The Endpoint In Qsys - Altera Cyclone V User Manual

Chapter 2: Getting Started

Qsys Design Flow

Qsys Design Flow
This section guides you through the steps necessary to customize the Cyclone V Hard
IP for PCI Express and run the example testbench in Qsys. It includes the following
steps:
■

Customizing the Endpoint in Qsys

Understanding the Files Generated
■
■ Generating the Simulation Model Using Qsys
■ Compiling the Design in the Qsys Design Flow
■ Modifying the Example Design
Customizing the Endpoint in Qsys
This section begins with the steps necessary to customize the Cyclone V Hard IP for
PCI Express. This section also guides you through steps to connect the chaining DMA
component testbench.
f
For further details about the parameter settings, refer to
Settings.
Follow these steps to instantiate the Cyclone V Hard IP for PCI Express and chaining
DMA example design using the Qsys design flow:
1. Create a directory for your project. This example uses <working_dir>/pcie_qsys.
2. To start Qsys from the Quartus II software, on the File menu click New.
3. In the New dialog box, click Qsys System File, then click OK. Qsys appears.
4. On the Project Settings tab specify the settings listed in
Table 2–8. Project Settings Parameters
Device family
Clock crossing adapter type
Limit interconnect pipeline stages to
Generation ID
Note to
(1) This setting applies to designs that include Avalon-MM interfaces.
5. On the Component Library tab, type the following text string in the search box:
PCI Ex r
6. Click on Cyclone V Hard IP for PCI Express and then click the +Add button. The
parameter editor appears.
November 2011 Altera Corporation
Parameter
Table 2–8:
Qsys filters the component library and shows all components matching the text
string you entered.
Chapter 3, Parameter
Cyclone V
Handshake
(1)
0
0
Table 2–8
Value
Cyclone V Hard IP for PCI Express
User Guide
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