Jtag Chain Control Or Pci Express Control Dip Switch; Fpga Configuration Mode Dip Switch; Cpu Reset Push Button - Altera Cyclone V Reference Manual

2–18

JTAG Chain Control or PCI Express Control DIP Switch

FPGA Configuration Mode DIP Switch

CPU Reset Push Button

Cyclone V GT FPGA Development Board
Reference Manual
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The JTAG chain control DIP switch (SW3) either remove or include devices in the
active JTAG chain. The Cyclone V GT FPGA is always in the JTAG chain. This switch
also enables or disables different link width configurations for the PCI Express
connector. Table 2–9 lists the switch controls and its descriptions.
Table 2–9. JTAG Chain Control DIP Switch
Switch
Schematic Signal Name
Position
1
PCIe_PRSNT2n_X1
2
PCIe_PRSNT2n_X4
3
HSMB_JTAG_EN
4
HSMA_JTAG_EN
The FPGA configuration mode DIP switch (SW5) defines the mode to use to configure
the FPGA. Table 2–10 lists the switch controls and its descriptions.
Table 2–10. FPGA Configuration Mode DIP Switch
Switch
Schematic Signal Name
Position
1
FPGA_MSEL1
2
FPGA_MSEL2
3
FPGA_MSEL4
4
FORCE_FAN
The CPU reset push button, CPU_RESETn (S4), is an input to the Cyclone V GT DEV_CLRn
pin and is an open-drain I/O from the MAX V CPLD System Controller. This push
button is the default reset for both the FPGA and CPLD logic. The MAX V CPLD
5M2210 System Controller also drives this push button during power-on-reset (POR).
Description
ON: PCI Express edge connector in-chain and enable x1
presence detect
OFF: Bypass PCI Express edge connector
ON: PCI Express edge connector in-chain and enable x4
presence detect
OFF: Bypass PCI Express edge connector
ON: Bypass HSMC port B
OFF: HSMC port B in-chain
ON: Bypass HSMC port A
OFF: HSMC port A in-chain
Description
ON: Select logic 0
OFF: Select logic 1
ON: Select logic 0
OFF: Select logic 1
ON: Select logic 0
OFF: Select logic 1
Optional fan control function to add into the MAX V CPLD
System Controller.
Not used by default.
Chapter 2: Board Components
Setup Elements
August 2017 Altera Corporation