Chapter 4. Ip Core Architecture - Altera Cyclone V User Manual

November 2011
1101
This chapter describes the architecture of the Cyclone V Hard IP for PCI Express. The
Cyclone V Hard IP for PCI Express implements the complete PCI Express protocol
stack as defined in the
the following layers:
■ Transaction Layer—The Transaction Layer contains the Configuration Space, the RX
and TX channels, the RX buffer, and flow control credits.
■ Data Link Layer—The Data Link Layer, located between the Physical Layer and the
Transaction Layer, manages packet transmission and maintains data integrity at
the link level. Specifically, the Data Link Layer performs the following tasks:
■
■
■
■
Physical Layer—The Physical Layer initializes the speed, lane numbering, and lane
■
width of the PCI Express link according to packets received from the link and
directives received from higher layers.
Figure 4–1
Express.
As Figure 4–1
Layer.
Table 4–1. Application Layer Clock Frequencies
×1
×4
The following interfaces provide access to the Application Layer's Configuration
Space Registers:
■ The LMI interface
■ For Root Ports, you can also access the Configuration Space Registers with a
Configuration Type TLP using the Avalon-ST interface. A Type 0 Configuration
TLP is used to access the Root Port Configuration Space Registers, and a Type 1
Configuration TLP is used to access the Configuration Space Registers of
downstream components, typically Endpoints on the other side of the link.
The Hard IP includes dedicated clock domain crossing logic (CDC) between the
PHYMAC and Data Link Layers.
November 2011 Altera Corporation
PCI Express Base Specification 2.1.
Manages transmission and reception of Data Link Layer Packets (DLLPs)
Generates all transmission cyclical redundancy code (CRC) values and checks
all CRCs during reception
Manages the retry buffer and retry mechanism according to received
ACK/NAK Data Link Layer packets
Initializes the flow control mechanism for DLLPs and routes flow control
credits to and from the Transaction Layer
provides a high-level block diagram of the Cyclone V Hard IP for PCI
illustrates, an Avalon-ST interface provides access to the Application
Table 4–1 provides the Application Layer clock frequencies.
Lanes
4. IP Core Architecture
The protocol stack includes
Gen1
125 MHz @ 64 bits or
62.5 MHz @ 64 bits
125 MHz @ 64 bits
Cyclone V Hard IP for PCI Express