Generating The Simulation Model Using Qsys - Altera Cyclone V User Manual

2–16
Figure 2–6
Figure 2–6. Complete Gen1 ×4 Endpoint (DUT) Connected to Example Design (APPS)

Generating the Simulation Model Using Qsys

Follow these steps to generate a simulation model that you can include in your own
PCI Express testbench.
1. On the Qsys Generation tab, specify the parameters listed in
Table 2–18. Parameters to Specify on the Generation Tab in Qsys (Part 1 of 2)
Parameter
Create simulation model
Create testbench Qsys system
Create testbench simulation model
Create HDL design files for synthesis
Create block symbol file (.bsf)
Path
Simulation
Testbench
Cyclone V Hard IP for PCI Express
illustrates the complete Qsys system.
Simulation
Verilog
(1)
Standard, BFMs for standard Avalon interfaces or None
(1)
Verilog or None
Synthesis
Turn on this option
Turn on this option
Output Directory
pcie_qsys/pcie_de_gen1_x4_ast64
pcie_qsys/pcie_de_gen1_x4_ast64/simulation
pcie_qsys/pcie_de_gen1_x4_ast64/testbench
Hard IP for PCI Express
Value
Chapter 2: Getting Started
Qsys Design Flow
Table 2–18.
November 2011 Altera Corporation