Clocks And Reset; Local Management Interface (Lmi Interface); Interrupts - Altera Cyclone V User Manual

Chapter 4: IP Core Architecture
Key Interfaces
The Application Layer may track credits consumed and use the credit limit
information to calculate the number of credits available. However, to enforce the PCI
Express Flow Control (FC) protocol, the Hard IP also checks the available credits
before sending a request to the link, and if the Application Layer violates the available
credits for a TLP it transmits, the Hard IP blocks that TLP and all future TLPs until
credits become available. By tracking the credit consumed information and
calculating the credits available, the Application Layer can optimize performance by
selecting for transmission only the TLPs that have credits available. Refer to
ST TX Interface" on page 5–8

Clocks and Reset

The
refclk in this design. Although the PCI Express Base Specification stipulates that the
frequency of this clock be 100 MHz, the Hard IP also accepts a 125 MHz reference
clock as a convenience. You can specify the frequency of your input reference clock
using the parameter editor under the System Settings heading.
The
■ cold reset—A hardware mechanism for setting or returning all port states to the
initial conditions following the application of power.
■ warm reset—A hardware mechanism for setting or returning all port states to the
initial conditions without cycling the supplied power.
hot reset —A reset propagated across a PCIe link using a Physical Layer
■
mechanism.
The PCI Express Base Specification also requires a system configuration time of 100 ms.
To meet this specification, the Cyclone V Hard IP for PCI Express includes an
embedded hard reset controller. For more information about clocks and reset, refer to
the "Clock Signals" on page 5–14

Local Management Interface (LMI Interface)

The LMI bus provides access to the PCI Express Configuration Space in the
Transaction Layer. For more LMI details, refer to

Interrupts

The Cyclone V Hard IP for PCI Express offers three interrupt mechanisms:
■ Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's
request-acknowledge handshaking protocol to implement interrupts. The MSI
Capability structure is stored in the Configuration Space and is programmable
using Configuration Space accesses.
■ MSI-X—The Transaction Layer generates MSI-X messages which are single dword
memory writes. In contrast to the MSI capability structure, which contains all of
the control and status information for the interrupt vectors, the MSI-X Capability
structure points to an MSI-X table structure and MSI-X PBA structure which are
stored in memory.
November 2011 Altera Corporation
PCI Express Base Specification
PCI Express Base Specification
for more information about the signals in this interface.
requires an input reference clock, which is called
2.1, requires the following three reset types:
and "Reset Signals" on page
"LMI Signals" on page
4–3
"Avalon-
5–14.
5–27.
Cyclone V Hard IP for PCI Express
User Guide