Avalon-St Tx Interface - Altera Cyclone V User Manual

5–8
Figure 5–8
with no idle cycles between the assertion of rx_st_eop and rx_st_sop.
Figure 5–8. 64-Bit Avalon-ST Interface Back-to-Back Transmission
coreclkout
C. C. C. C. CCCC008347890. C. C. C. C. C. C. C. C.
rx_st_data[63:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_ready
rx_st_valid
f
For a complete description of the TLP packet header formats, refer to
Transaction Layer Packet (TLP) Header

Avalon-ST TX Interface

Table 5–4
signal can be 64 or 128 bits.
Table 5–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 1 of 3)
Signal
tx_st_data
tx_st_sop
tx_st_eop
Cyclone V Hard IP for PCI Express
illustrates back-to-back transmission on the 64-bit Avalon-ST RX interface
describes the signals that comprise the Avalon-ST TX Datapath. The TX data
Avalon-ST
Width Dir
Type
64 I
data
start of
1 I
packet
end of
1 I
packet
C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C.
Formats.
Description
Data for transmission. Transmit data bus. Refer to
Figure 5–9 through Figure 5–13
packets to tx_st_data and examples of the timing of the
64-bit interface.
The Application Layer must provide a properly formatted
TLP on the TX interface. The mapping of message TLPs is
the same as the mapping of Transaction Layer TLPs with 4
dword headers. The number of data cycles must be correct
for the length and address fields in the header. Issuing a
packet with an incorrect number of data cycles results in
the TX interface hanging and unable to accept further
requests.
Indicates first cycle of a TLP when asserted in the same
cycle with tx_st_valid.
Indicates last cycle of a TLP when asserted in the same
cycle with tx_st_valid.
Chapter 5: IP Core Interfaces
Avalon-ST TX Interface
Appendix A,
for the mapping of TLP
November 2011 Altera Corporation