Configuring The Max V Device To Program Epcq; Fpga Configuration; Fpga Programming Over Embedded Usb-Blaster - Altera Cyclone V Reference Manual

Chapter 2: Board Components

Configuring the MAX V Device to Program EPCQ

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 5)
Board
Reference (U32)
P8
T7
N8
R8
T8
T9
R9
P9
M8
T10
H5
Configuring the MAX V Device to Program EPCQ

FPGA Configuration

FPGA Programming over Embedded USB-Blaster

August 2017 Altera Corporation
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Schematic Signal Name I/O Standard
USB_CFG2
USB_CFG3
USB_CFG4
USB_CFG5
USB_CFG6
USB_CFG7
USB_CFG8
USB_CFG9
USB_CFG10
USB_CFG11
USB_CLK
It is possible to configure the FPGA from the EPCQ device. However, the MAX V
design provided with the Cyclone V GT FPGA development kit does not allow you to
store a design in the EPCQ configuration device.
To enable FPGA configuration using the EPCQ device, reconfigure the MAX V device
with the design file found at
Cyclone V GT FPGA Development
The Cyclone V GT development board supports the following three configuration
methods:
■ Embedded USB-Blaster II is the default method for configuring the FPGA using
the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the program configuration
push button (S6).
External USB-Blaster for configuring the FPGA using an external USB-Blaster that
■
connects to the JTAG chain header (J13).
This configuration method implements a type-B mini USB connector (J5), a USB 2.0
PHY device (U4), and an Altera MAX II CPLD EPM570GT100C3N (U49) to allow
FPGA configuration using a USB cable. This USB cable connects directly between the
USB connector on the board and a USB port of a PC running the Quartus II software.
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
1.8-V Embedded USB-Blaster II interface. Reserved for future use
2.5-V Embedded USB-Blaster II interface clock
How do I access the EPCQ configuration device on the
Kit?.
Description
Cyclone V GT FPGA Development Board
Reference Manual
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