Key Interfaces; Avalon-St Interface; Rx Datapath; Tx Datapath - Altera Cyclone V User Manual

4–2
This chapter provides an overview of the architecture of the Cyclone V Hard IP for
PCI Express. It includes the following sections:

Key Interfaces

■
Protocol Layers
■
■ Multi-Function Support
Key Interfaces
The following sections introduce the functionality of the interfaces shown in
Figure
.
Figure 4–1. Block Diagram
Clocks and Reset

Avalon-ST Interface

An Avalon-ST interface connects the Application Layer and the Transaction Layer.
This is a point-to-point, streaming interface designed for high throughput
applications. The Avalon-ST interface includes the RX and TX datapaths.
f
For more information about the Avalon-ST interface, including timing diagrams, refer
to the

RX Datapath

The RX datapath transports data from the Transaction Layer to the Application
Layer's Avalon-ST interface. Masking of non-posted requests is partially supported.
Refer to the description of the rx_st_mask signal for further information about
masking. For more detailed information about the RX datapath, refer to
RX Interface" on page

TX Datapath

The TX datapath transports data from the Application Layer's Avalon-ST interface to
the Transaction Layer. The Hard IP provides credit information to the Application
Layer for posted headers, posted data, non-posted headers, non-posted data,
completion headers and completion data.
Cyclone V Hard IP for PCI Express
4–1.
Altera FPGA
Hard IP for
PCI Express
Avalon-ST
LMI
Interrupts
Avalon Interface Specifications.
5–3.
PHY IP Core for
PCI Express (PIPE)
PIPE Interface
Transceiver
Reconfiguration
PCS
Chapter 4: IP Core Architecture
Key Interfaces
PMA
"Avalon-ST
November 2011 Altera Corporation