Flash - Altera Cyclone V Reference Manual

Chapter 2: Board Components
Memory

Flash

Table 2–30. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference (U20)
F6
B4
E6
F8
F7
D4
G8
C6
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
August 2017 Altera Corporation
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The development board supports a 1-GB CFI-compatible synchronous flash device for
non-volatile storage of FPGA configuration data, board information, test application
data, and user code space. This device is part of the shared FM bus that connects the
flash memory and MAX V CPLD 5M2210 System Controller.
This 16-bit data interface can sustain burst read operations at up to 52 MHz for a
throughput of 832 Mbps per device. The write performance is 270 µs for a single word
buffer while the erase time is 800 ms for a 128 K array block.
Table 2–30 lists the flash pin assignments, signal names, and functions. The signal
names and types are relative to the Cyclone V GT in terms of I/O setting and
direction.
Schematic Signal Name
FLASH_ADVN
FLASH_CEN
FLASH_CLK
FLASH_OEN
FLASH_RDYBSYN
FLASH_RESETN
FLASH_WEN
FLASH_WPN
FSM_A1
FSM_A2
FSM_A3
FSM_A4
FSM_A5
FSM_A6
FSM_A7
FSM_A8
FSM_A9
FSM_A10
FSM_A11
FSM_A12
FSM_A13
FSM_A14
FSM_A15
FSM_A16
FSM_A17
FSM_A18
FSM_A19
FSM_A20
Cyclone V GT
I/O Standard
Pin Number
AB34 2.5-V
AA21 2.5-V
AE29 2.5-V
AG16 2.5-V
AD20 2.5-V
AB16 2.5-V
AM14 2.5-V
— 2.5-V
AK33 2.5-V
AC27 2.5-V
AB24 2.5-V
AB23 2.5-V
AC28 2.5-V
Y24 2.5-V
Y25 2.5-V
AF27 2.5-V
AF26 2.5-V
AB28 2.5-V
AE28 2.5-V
AB29 2.5-V
AF28 2.5-V
AH28 2.5-V
AB30 2.5-V
AG29 2.5-V
AA30 2.5-V
AK30 2.5-V
AJ30 2.5-V
AG30 2.5-V
Description
Address valid
Chip enable
Clock
Output enable
Ready
Reset
Write enable
Write protect
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Cyclone V GT FPGA Development Board
Reference Manual
2–49