General User Input/Output; User-Defined Push Buttons - Altera Cyclone V Reference Manual

2–22
Table 2–12. Off-Board Clock Inputs (Part 2 of 2)
Source
Samtec HSMC
PCI Express
Edge
Table 2–13. Off-Board Clock Outputs
Source
LVDS SMA
Samtec HSMC
Samtec HSMC
SMA

General User Input/Output

User-Defined Push Buttons

Cyclone V GT FPGA Development Board
Reference Manual
Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from Downloaded from
Schematic Signal
I/O Standard
Name
2.5-V
HSMB_CLK_IN0
LVDS/2.5-V
HSMB_CLK_IN_P1
LVDS/LVTTL
HSMB_CLK_IN_N1
LVDS/LVTTL
HSMB_CLK_IN_P2
LVDS/LVTTL
HSMB_CLK_IN_N2
HCSL
PCIE_REFCLK_P
HCSL
PCIE_REFCLK_N
Table 2–13 lists the clock outputs for the development board.
Schematic Signal
I/O Standard
Name
LVPECL
CLKOUT_SMA_P
LVPECL
CLKOUT_SMA_N
2.5V CMOS
HSMA_CLK_OUT0
LVDS/2.5V CMOS
HSMA_CLK_OUT_P1
LVDS/2.5V CMOS
HSMA_CLK_OUT_N1
LVDS/2.5V CMOS
HSMA_CLK_OUT_P2
LVDS/2.5V CMOS
HSMA_CLK_OUT_N2
2.5V CMOS
HSMB_CLK_OUT0
LVDS/2.5V CMOS
HSMB_CLK_OUT_P1
LVDS/2.5V CMOS
HSMB_CLK_OUT_N1
LVDS/2.5V CMOS
HSMB_CLK_OUT_P2
LVDS/2.5V CMOS
HSMB_CLK_OUT_N2
2.5V CMOS
SMA_CLKOUT
This section describes the user I/O interface to the FPGA, including the push buttons,
DIP switches, LEDs, and character LCD.
The development board includes three user-defined push buttons. For information on
the system and safe reset push buttons, refer to
Board references S1, S2, and S3 are push buttons for controlling the FPGA designs that
loads into the Cyclone V GT device. When you press and hold down the switch, the
device pin is set to logic 0; when you release the switch, the device pin is set to logic 1.
There are no board-specific functions for these general user push buttons.
Cyclone V GT
Pin Number
Single-ended input from the installed HSMC cable
A22
or board.
K25
LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
J25
J20
LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
K19
W11
HCSL input from the PCI Express edge connector.
V10
Cyclone V GT
Pin Number
—
Driven from LVDS clock buffer U3
—
F10 FPGA CMOS output (or GPIO)
C1
LVDS output. Can also support 2x CMOS
outputs.
B1
B18
LVDS output. Can also support 2x CMOS
outputs.
A18
D25 FPGA CMOS output (or GPIO)
L22
LVDS output. Can also support 2x CMOS
outputs.
K22
F26
LVDS output. Can also support 2x CMOS
outputs.
G26
AF33 FPGA CMOS output (or GPIO)
"Setup Elements" on page
Chapter 2: Board Components
General User Input/Output
Description
Description
2–17.
August 2017 Altera Corporation