Protocol Layers; Transaction Layer - Altera Cyclone V User Manual

4–4
■ Legacy interrupts—The app_int_sts input port controls legacy interrupt
generation. When app_int_sts is asserted, the Hard IP generates an
Assert_INT<n> message TLP. For more detailed information about interrupts,
refer to

Protocol Layers

This section describes the Transaction Layer, Data Link Layer, and Physical Layer in
more detail.

Transaction Layer

The Transaction Layer is located between the Application Layer and the Data Link
Layer. It generates and receives Transaction Layer Packets.
Transaction Layer. As
sub-blocks: the TX datapath, the Configuration Space, and the RX datapath.
Figure 4–2. Architecture of the Transaction Layer: Dedicated Receive Buffer
Transaction Layer TX Datapath
Avalon-ST
Width
TX Data
Adapter
( <256
bits)
Transaction Layer RX Datapath
Avalon-ST RX Data
Avalon-ST
RX Control
Tracing a transaction through the RX datapath includes the following steps:
1. The Transaction Layer receives a TLP from the Data Link Layer.
2. The Transaction Layer determines whether the TLP is well formed and directs the
packet based on traffic class (TC).
Cyclone V Hard IP for PCI Express
"Interrupt Signals for Endpoints" on page
Figure 4–2
to Application Layer
TX Flow
Control
Packet
Alignment
Configuration Space
RX
Control
Reordering
5–17.
illustrates, the Transaction Layer includes three
TX
Control
Configuration Requests
RX Buffer
Posted & Completion
Non-Posted
Transaction Layer
Packet FIFO
Flow Control Update
Chapter 4: IP Core Architecture
Protocol Layers
Figure 4–2 illustrates the
TLPs to
Data Link Layer
RX Transaction
Layer Packet
November 2011 Altera Corporation