Debug Features - Altera Cyclone V User Manual

1–4
Optimized for Altera devices, the Cyclone V Hard IP for PCI Express supports all
memory, I/O, configuration, and message transactions. It has a highly optimized
Application Layer interface to achieve maximum effective throughput. You can
customize the Hard IP to meet your design requirements using either the
MegaWizard Plug-In Manager or the Qsys design flow.
Figure 1–1
configured as a Root Port and the other as an Endpoint.
Figure 1–1. PCI Express Application with a Single Root Port and Endpoint
Altera FPGA
User Application
Logic
Figure 1–2
a Root Port and the other as a multi-function Endpoint. The FPGA serves as a custom
I/O hub for the host CPU. In the Cyclone V FPGA, each peripheral is treated as a
function with its own set of Configuration Space registers. Eight multiplexed
functions operate using a single PCI Express link.
Figure 1–2. PCI Express Application with an Endpoint Using the Multi-Function Capability
Altera FPGA
Memory
Controller
Peripheral
Controller
Peripheral
Controller

Debug Features

The Cyclone V Hard IP for PCI Express includes debug features that allow
observation and control of the Hard IP for faster debugging of system-level problems.
For more information about debugging refer to
Cyclone V Hard IP for PCI Express
shows a PCI Express link between two Cyclone V FPGAs. One is
PCIe
Hard IP
PCI Express Link
RP
shows a PCI Express link between two Altera FPGAs. One is configured as
PCIe
Hard IP
Host
CPU PCI Express Link
RP
Altera FPGA
PCIe
Hard IP
User Application
Logic
EP
Altera V FPGA
CAN GbE ATA
PCIe Hard
IP Multi-
Function
EP
USB SPI GPIO
Chapter 15, Debugging.
November 2011 Altera Corporation
Chapter 1: Datasheet
Debug Features
PCI
I2C