Sdi Video Input - Altera Cyclone V Reference Manual

Gt fpga development board

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Table Of Contents

Table of Contents

Chapter 2: Board Components

Components and Interfaces

Table 2–27. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions

Board

Reference (U47)

August 2017 Altera Corporation

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SDI Video Input

The cable equalizer supports operation at 270 Mb SD, 1.5 Gb HD, and 2.97 Gb dual-

link HD modes. Control signals are allowed for bypassing or disabling the device, as

well as a carrier detect or auto-mute signal interface.

Table 2–26

lists the cable equalizer lengths.

Table 2–26. SDI Cable Equalizer Lengths

Data Rate (Mbps)

270

1485

2970

Figure 2–9

shows the SDI cable equalizer, which is an excerpt from the LMH0384

cable equalizer data sheet. On this development board, the output is a single-ended

output, with the negative channel driving a load local to the board.

Figure 2–9. SDI Cable Equalizer

Coaxial Cable

5.6 nH

MUTE

REF

BYPASS

Table 2–27

summarizes the SDI video input interface pin assignments, signal names,

and functions.

Schematic Signal Name

SDI_A_IN_P1

SDI_A_EQIN_N1

SDI_A_RX_BYPASS

SDI_A_RX_N

SDI_A_RX_P

SDI_A_RX_EN

Cable Type

Belden 1694A

1.0 μF

75 Ω

SDI

1.0 μF

SDI

75 Ω

37.4 Ω

MUTE

BYPASS

Cyclone V GT

I/O Standard

Pin Number

—

2.5-V

—

2.5-V

AM9

2.5-V

1.5-V PCML

AN4

2.5-V

Maximum Cable Length (m)

400

140

120

SDI Adaptive

Cable Equalizer

SDO

To FPGA

SDO

REF

1.0 μF

Description

Serial data

Equalizer bypass enable

Serial data input N

Serial data input P

Device enable

Cyclone V GT FPGA Development Board

Reference Manual

2–37

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Sdi Video Input - Altera Cyclone V Reference Manual

SDI Video Input

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