Configuration Space Register Access - Altera Cyclone V User Manual

5–24

Configuration Space Register Access

The tl_cfg_ctl signal is a multiplexed bus that contains the contents of
Configuration Space registers as shown in
Configuration Space is accessed in round robin order where tl_cfg_add indicates
which register is being accessed.
information that is multiplexed on tl_cfg_ctl.
Table 5–13. Multiplexed Configuration Register Information Available on tl_cfg_ctl
Address 31:24
cfg_devcsr_func<n>[15:0]
0
cfg_devcsr[14:12]=
Max Read Req Size
1
2
3
8'h00
4
5
cfg_msi_addr[11:0]
6
cfg_msi_addr[43:32]
7
8h'00
8
9
A
B
C
D
tx_ecrcgen[25],
E
rx_ecrccheck[24]
F
Notes to Table 5–13:
(1) Items in blue are only available for Root Ports.
(2) This field is encoded as specified in Section 7.8.4 of the
(3) rx_ecrccheck and tx_ecrcgen are bit s 24 and 25 of tl_cfg_ctl, respectively. (Other bit specifications in this table indicate the bit location
within the Configuration Space register.)
Table 5–14
Table
Table 5–14. Configuration Space Register Descriptions (Part 1 of 3)
Width
Register
cfg_devcsr_func<n>
cfg_dev2csr
Cyclone V Hard IP for PCI Express
23:16
cfg_devcsr[7:5]=
(2)
Max Payload
cfg_linkscr[15:0]
cfg_prmcsr_func<n>[15:0]
cfg_seccsr[15:0]
cfg_np_bas[11:0]
cfgi_msi_addr[31:12]
cfg_msi_addr[63:44]
cfg_msixcsr[15:0]
(3)
cfg_msi_data[15:0]
PCI Express Base
describes the Configuration Space registers referred to in
5–13.
Dir
cfg_devcsr_func<n>[31:16]is status and
32 O cfg_devcsr[15:0] is Device Control for the PCI Express
capability structure.
cft_dev2csr[31:16] is status 2 and cfg_dev2csr[15:0]
32 O
is device control 2 for the PCI Express capability structure.
Transaction Layer Configuration Space Signals
Table 5–11. Information stored in the
Table 5–13 shows the layout of configuration
15:8
cfg_dev2csr[15:0]
(2)
cfg_slotcsr[15:0]
cfg_link2csr[15:0]
cfg_secbus[7:0]
cfg_io_bas[19:0]
cfg_io_lim[19:0]
cfg_pr_bas[31:0]
cfg_pr_lim[31:0]
cfg_pmcsr[31:0]
cfg_msicsr[15:0]
cfg_tcvcmap[23:0]
3'b000
Specification. (3'b000–3'b101 correspond to 128–4096 bytes).
Description
Chapter 5: IP Core Interfaces
(1)
7:0
cfg_rootcsr[7:0]
cfg_subbus[7:0]
cfg_np_lim[11:0]
cfg_pr_bas[43:32]
cfg_pr_lim[43:32]
cfg_busdev[12:0]
Table 5–11
Register
Reference
Table 6–7 on
page 6–4
Table 6–8 on
page 6–4
November 2011 Altera Corporation
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