Featured Device: Cyclone V Gt Fpga; I/O Resources - Altera Cyclone V Reference Manual

Chapter 2: Board Components

Featured Device: Cyclone V GT FPGA

Table 2–1. Board Components (Part 4 of 4)
Board Reference
SW2
J15
Featured Device: Cyclone V GT FPGA

I/O Resources

Table 2–3. Cyclone V GT Device I/O Pin Count
DDR3A
DDR3B
MAX V System Controller
Flash
PCI Express x4 port
HSMA port
HSMB port
Gigabit Ethernet port
On-Board USB-Blaster II
August 2017 Altera Corporation
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Type
Power switch
Fan power
The Cyclone V GT FPGA development board features a Cyclone V GT
5CGTFD9E5F35C7N device in a 1152-pin FBGA package.
f
For more information about Cyclone V device family, refer to the
Handbook.
Table 2–2 describes the features of the Cyclone V GT 5CGTFD9E5F35C7N device.
Table 2–2. Cyclone V GT Features
Resource
LEs (K)
ALMs
Register
Memory (Kb)
18-bit × 18-bit Multiplier
PLLs
Transceivers (6 Gbps)
The Cyclone V GT 5CGTFD9E5F35C7N device has total of 560 user I/Os and 12
transceiver channels.
by function on the board.
Function
1.2-V–2.5-V CMOS DQ/DQS
Switch to power on or off the board when power is supplied from the
DC input jack.
Fan power header.
5CGTFD9E5F35C7N
301
113,560
454,240
M10K 12,200
MLAB 1,717
684
8
12
Table 2–3 lists the Cyclone V GT device I/O pin count and usage
I/O Standard I/O Count
1.5-V SSTL
1.5-V SSTL
1.8-V CMOS
1.8-V CMOS
2.5-V CMOS
2.5-V CMOS + LVDS
(Default: 2.5-V)
2.5-V CMOS + LVDS
1.5-V or 2.5-V CMOS
Description
Cyclone V Device
Special Clock Pins
81 —
114 —
4 —
49 —
8 One reference clock
87 —
88 —
16 —
19 —
Cyclone V GT FPGA Development Board
Reference Manual
2–5