Max V Cpld 5M2210 System Controller - Altera Cyclone V Reference Manual

2–6
Table 2–3. Cyclone V GT Device I/O Pin Count
SDI video port
Push buttons
DIP switches
Character LCD
LEDs
SMA
Clock or Oscillators
ASSP
Configuration
Total I/O Used:

MAX V CPLD 5M2210 System Controller

Cyclone V GT FPGA Development Board
Reference Manual
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Function
Table 2–4 lists the Cyclone V GT device transceiver count and usage by function on
the board.
Table 2–4. Cyclone V GT Transceivers
Function
HSMA port
HSMA port or SDI (supports HSMA by default)
HSMB port
PCI Express x4 port
Total Transceivers
The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the
following purposes:
■ FPGA configuration from flash
■ Power measurement
■ Control and status registers (CSRs) for remote system update
I/O Standard I/O Count
2.5-V CMOS + XCVR
1.5-V CMOS
1.5-V CMOS
1.5-V CMOS
1.5-V CMOS
CMOS
1.8-V CMOS + LVDS
1.5-V CMOS
—
Count
Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
Special Clock Pins
6 —
4 —
8 —
2 —
8 —
1 —
Four differential clocks, 1
9
1 single-ended
8 —
30 —
540
3
1
4
4
12
August 2017 Altera Corporation