Completion Side Band Signals - Altera Cyclone V User Manual

Chapter 5: IP Core Interfaces

Completion Side Band Signals

Completion Side Band Signals
Table 5–10
Avalon-ST interface. The Cyclone V Hard IP for PCI Express provides a completion
error interface that the Application Layer can use to report errors, such as
programming model errors. When the Application Layer detects an error, it can assert
the appropriate cpl_err bit to indicate what kind of error to log. The Hard IP sets the
appropriate status bits for the errors in the Configuration Space, and automatically
sends error messages in accordance with the
the Application Layer is responsible for sending the completion with the appropriate
completion status value for non-posted requests. Refer to
for information on errors that are automatically detected and handled by the Hard IP.
f
For a description of the completion rules, the completion header format, and
completion status field values, refer to Section 2.2.9 of the
Specification, Rev.
Table 5–10. Completion Signals for the Avalon-ST Interface (Part 1 of 2)
Signal
cpl_err[6:0]
November 2011 Altera Corporation
describes the signals that comprise the completion side band signals for the
2.1.
I/O
Completion error. This signal reports completion errors to the Configuration
Space. When an error occurs, the appropriate signal is asserted for one cycle.
cpl_err[0]: Completion timeout error with recovery. This signal should be
■
asserted when a master-like interface has performed a non-posted request
that never receives a corresponding completion transaction after the 50 ms
timeout period when the error is correctable. The Hard IP automatically
generates an advisory error message that is sent to the Root Complex.
cpl_err[1]: Completion timeout error without recovery. This signal should
■
be asserted when a master-like interface has performed a non-posted request
that never receives a corresponding completion transaction after the 50 ms
time-out period when the error is not correctable. The Hard IP automatically
generates a non-advisory error message that is sent to the Root Complex.
cpl_err[2]:Completer abort error. The Application Layer asserts this signal
■
to respond to a posted or non-posted request with a Completer Abort (CA)
completion. In the case of a non-posted request, the Application Layer
generates and sends a completion packet with Completer Abort (CA) status to
I
the requestor and then asserts this error signal to the Hard IP. The Hard IP
automatically sets the error status bits in the Configuration Space register and
sends error messages in accordance with the
Specification, Rev. 2.1 .
cpl_err[3]: Unexpected completion error. This signal must be asserted
■
when an Application Layer master block detects an unexpected completion
transaction. Many cases of unexpected completions are detected and reported
internally by the Transaction Layer. For a list of these cases, refer to
"Transaction Layer Errors" on page
cpl_err[4]: Unsupported Request (UR) error for posted TLP. The
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Application Layer asserts this signal to treat a posted request as an
Unsupported Request. The Hard IP automatically sets the error status bits in
the Configuration Space register and sends error messages in accordance
with the PCI Express Base Specification
Requests are detected and reported internally by the Transaction Layer. For a
list of these cases, refer to
PCI Express Base Specification. Note that
Chapter 12, Error Handling
PCI Express Base
Description
PCI Express Base
12–3.
. Many cases of Unsupported
"Transaction Layer Errors" on page
Cyclone V Hard IP for PCI Express
5–19
12–3.
User Guide