Data Link Layer - Altera Cyclone V User Manual

Hard ip for pci express
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4–6

Data Link Layer

The Data Link Layer (DLL) is located between the Transaction Layer and the Physical
Layer. It maintains packet integrity and for communicates (by DLL packet
transmission) at the PCI Express link level (as opposed to component communication
by TLP transmission in the interconnect fabric).
The DLL implements the following functions:
Link management through the reception and transmission of DLL packets (DLLP),
which are used for the following functions:
Data integrity through generation and checking of CRCs for TLPs and DLLPs
TLP retransmission in case of NAK DLLP reception using the retry buffer
Management of the retry buffer
Link retraining requests in case of error through the Link Training and Status State
Machine (LTSSM) of the Physical Layer
Figure 4–3
Figure 4–3. Data Link Layer
To Transaction Layer
Tx Transaction Layer
Packet Description & Data
Configuration Space
Tx Flow Control Credits
Rx Flow Control Credits
Rx Transation Layer
Packet Description & Data
Cyclone V Hard IP for PCI Express
For power management of DLLP reception and transmission
To transmit and receive ACK/NACK packets
illustrates the architecture of the DLL.
Transaction Layer
Packet Generator
Retry Buffer
Ack/Nack
Packets
Transaction Layer
Packet Checker
Tx Arbitration
DLLP
Generator
Data Link Control
Power
and Management
Management
State Machine
Function
DLLP
Checker
Chapter 4: IP Core Architecture
Protocol Layers
To Physical Layer
Tx Packets
TX Datapath
Control
& Status
RX Datapath
Rx Packets
November 2011 Altera Corporation

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