Configuration Space Register Access Timing - Altera Cyclone V User Manual

Chapter 5: IP Core Interfaces
Transaction Layer Configuration Space Signals
Table 5–12. Mapping Between tl_cfg_sts and Configuration Space Registers (Part 2 of 2)
tl_cfg_sts[122:0]
[29:25]
cfg_prmcsr_func0[31:27]
[24]
cfg_prmcsr_func0[24]
[23:6]
cfg_rootcsr[25:8]
[5:1]
cfg_seccsr[31:27]
[0]
cfg_seccsr[24]

Configuration Space Register Access Timing

Figure 5–15
increments on the rising edge of coreclkout, specifying which Configuration Space
register information is being driven onto tl_cfg_ctl.
Figure 5–15. tl_cfg_ctl Timing
coreclkout
2 3
tl_cfg_add[3:0]
. . 00... 00...
tl_cfg_ctl[31:0]
November 2011 Altera Corporation
Correspondence
Records the following 5 primary command status errors:
■
■
■
■
■
Primary command status error bit, data parity reported.
Records the following PME status information:
■
■
■
Records the following 5 secondary command status errors:
■
■
■
■
■
6th primary command status error bit.
shows typical traffic on the tl_cfg_ctl bus. The tl_cfg_add index
4 5 6 7 8
00... 7F...
00000000
Description
Detected parity error
Received system error
Received master abort
Received target abort
Signalled target abort.
PME pending
PME status
PME request ID[15:0]
Detected parity error
Received system error
Received master abort
Received target abort
Signalled target abort
9 A B 8 9
00000000
A B C D E
00... 00...
Cyclone V Hard IP for PCI Express
User Guide
5–23