Off-Board Clock Input/Output - Altera Cyclone V Reference Manual

Chapter 2: Board Components
Clock Circuitry
Table 2–11. On-Board Oscillators (Part 2 of 2)
Source
CLKINTOP_P
CLKINTOP_N
CLKINBOT_P
CLKINBOT_N
CLKIN_R_P
X4 to U3
CLKIN_R_N
REFCLK_QL1_P
REFCLK_QL1_N
REFCLK_QL3_P
REFCLK_QL3_N
SMA_CLKOUT_P
SMA_CLKOUT_N
REFCLK_QL2_P
X3
REFCLK_QL2_N
X1
ENET_XTAL_25MHZ

Off-Board Clock Input/Output

Table 2–12. Off-Board Clock Inputs (Part 1 of 2)
Source
SMA
Samtec HSMC
August 2017 Altera Corporation
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Schematic Signal
Frequency
Name
100.000 MHz
(Programmable
between 10–810 MHz)
148.500 MHz
(Programmable
between 10–810 MHz)
25.000 MHz
The development board has input and output clocks which can be driven onto the
board. The output clocks can be programmed to different levels and I/O standards
according to the FPGA device's specification.
Table 2–12 lists the clock inputs for the development board.
Schematic Signal
I/O Standard
Name
CLKIN_SMA_P
CLKIN_SMA_N
HSMA_CLK_IN0
LVDS/2.5-V
HSMA_CLK_IN_P1
LVDS/LVTTL
HSMA_CLK_IN_N1
LVDS/LVTTL
HSMA_CLK_IN_P2
LVDS/LVTTL
HSMA_CLK_IN_N2
I/O Standard
LVDS
(fanout
buffer)
LVDS
2.5-V CMOS
Cyclone V GT
Pin Number
LVPECL —
Input to LVDS fan-out buffer (drives two reference
clocks and three GPLL inputs)
LVPECL —
Single-ended input from the installed HSMC cable
2.5-V G11
or board.
G18
LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
F18
H17
LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
H16
Cyclone V GT
Application
Pin Number
Top edge (CLK10p) for general
H19
purpose logic
Top edge (CLK10n) for general
H18
purpose logic
AF18 Bottom edge (CLK2p)
AG18 Bottom edge (CLK2n)
Right edge (CLK7p) for general
W26
purpose logic
Right edge (CLK7n) for general
W27
purpose logic
AA11
Transceiver bank QL0 for PCI
Express edge connector
AB10
R11
Transceiver bank QL3 for
HSMC port B transceivers
P10
—
Oscilloscope trigger output
—
U11
SDI video or HSMC port A
transceivers
T10
Reference clock for the
—
Ethernet PHY
Description
Cyclone V GT FPGA Development Board
2–21
Reference Manual