Avalon-St Rx Interface - Altera Cyclone V User Manual

Chapter 5: IP Core Interfaces

Avalon-ST RX Interface

Avalon-ST RX Interface
Table 5–2
signal can be 64 or 128 bits.
Table 5–2. 64- or 128-Bit Avalon-ST RX Datapath (Part 1 of 2)
Signal
rx_st_data
rx_st_sop
rx_st_eop
rx_st_ready
rx_st_valid
rx_st_err
rx_st_mask
November 2011 Altera Corporation
describes the signals that comprise the Avalon-ST RX Datapath. The RX data
Avalon-ST
Width Dir
Type
64 O
data
start of
1 O
packet
end of
1 O
packet
1 I
ready
1 O
valid
1 O
error
Component Specific Signals
component
1 I
specific
Description
Receive data bus. Refer to the figures below for the mapping of
the Transaction Layer's TLP information to rx_st_data and
examples of the timing of this interface. Note that the position
of the first payload dword depends on whether the TLP address
is qword aligned. The mapping of message TLPs is the same as
the mapping of TLPs with 4 dword headers.
Indicates that this is the first cycle of the TLP when
rx_st_valid is asserted.
Indicates that this is the last cycle of the TLP when
rx_st_valid is asserted.
Indicates that the Application Layer is ready to accept data. The
Application Layer deasserts this signal to throttle the data
stream.
If rx_st_ready is asserted by the Application Layer on cycle
<n>, then <n + readyLatency> is a ready cycle, during which
the Transaction Layer may assert valid and transfer data.
The RX interface supports a readyLatency of 2 cycles.
Clocks rx_st_data into the Application Layer. Deasserts
within 2 clocks of rx_st_ready deassertion and reasserts
within 2 clocks of rx_st_ready the assertion if more data is
available to send.
Indicates that there is an uncorrectable ECC error in the internal
RX buffer. Active when ECC is enabled. ECC is automatically
enabled by the Quartus II assembler. ECC corrects single-bit
errors and detects double-bit errors on a per byte basis.
When an uncorrectable ECC error is detected, rx_st_err is
asserted for at least 1 cycle while rx_st_valid is asserted.
Altera recommends resetting the Cyclone V Hard IP for PCI
Express IP core when an uncorrectable (double-bit) ECC error
is detected.
The Application Layer asserts this signal to tell the Hard IP to
stop sending non-posted requests. This signal can be asserted
at any time. The total number of non-posted requests that can
be transferred to the Application Layer after rx_st_mask is
asserted is not greater than 10.
5–3
Cyclone V Hard IP for PCI Express
User Guide