Quartus Ii Compilation; Compiling The Design In The Megawizard Plug-In Manager Design Flow; Compiling The Design In The Qsys Design Flow - Altera Cyclone V User Manual

Chapter 2: Getting Started

Quartus II Compilation

Table 2–18. Parameters to Specify on the Generation Tab in Qsys (Part 2 of 2)
Parameter
Synthesis
Note to Table 2–18:
(1) You can generate a simulation testbench; however the Root Port BFM is not available in the current release. Simulation models are available for
Verilog HDL.
2. Click the Generate button at the bottom of the Generation tab to create the
chaining DMA simulation model, which you can include in your own custom
testbench.
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You can also generate the testbench which shows you the connections necessary
between the Endpoint and a Root Port BFM. However, the Root Port BFM is not
available for simulation in the current release.
Quartus II Compilation
This section provides step-by-step instructions for Quartus II compilation. To compile
your Endpoint and design example, complete the instructions in one of the following
two sections:
■

Compiling the Design in the MegaWizard Plug-In Manager Design Flow

■

Compiling the Design in the Qsys Design Flow

Compiling the Design in the MegaWizard Plug-In Manager Design Flow
To compile your design, on the Processing menu, select Start Compilation.
Compiling the Design in the Qsys Design Flow
To compile the Qsys design example in the Quartus II software, you must create a
Quartus II project and add your Qsys files to that project.
Complete the following steps to create your Quartus II project:
1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run
the Quartus II software.
2. Change to the directory that includes your Qsys project, <working_dir>\pcie_qsys.
3. On the Quartus II File menu, click New, then New Quartus II Project, then OK.
4. Click Next in the New Project Wizard: Introduction (The introduction does not
display if you previously turned it off.)
5. On the Directory, Name, Top-Level Entity page, enter the following information:
a. The working directory for your project. This design example uses
b. The name of the project. Type the same name as your Qsys design
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November 2011 Altera Corporation
pcie_qsys/pcie_de_gen1_x4_ast64/t/synthesis
<working_dir>/pcie_qsys
pcie_de_gen1_x4_ast64 r
If the top-level design entity and Qsys system names are identical, the
Quartus II software treats the Qsys system as the top-level design entity.
Value
Cyclone V Hard IP for PCI Express
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