Basic Operation Timing In Multiplex Extended Mode; Figure 6.13 Bus Timing For 8-Bit, 2-State Data Access Space (With Address Wait) - Renesas H8S/2437 Hardware Manual

6.5.4

Basic Operation Timing in Multiplex Extended Mode

8-Bit, 2-State Data Access Space:
Figures 6.13 and 6.14 show the bus timing for an 8-bit, 2-state access space. When an 8-bit access
space is accessed, the upper half (AD15 to AD8) of the address bus and the data bus is used. Wait
states cannot be inserted.
AD15 to AD8
Note: n = 1 to 3

Figure 6.13 Bus Timing for 8-Bit, 2-State Data Access Space (With Address Wait)

Read Cycle
Address Data
T T T T
1 AW 2 3
Address
Write Cycle
Address
T T T T
4 1 AW 2
Address
Data
Rev. 1.00, 09/03, page 113 of 704
Data
T T
3 4
Data