Figure 10.26 Receive Data Sampling Timing In Asynchronous Mode - Renesas H8/3847R Series Hardware Manual

Section 10 Serial Communication Interface
0
Internal
basic clock
Receive data
(RXD3x)
Synchronization
sampling timing
Data sampling
timing

Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode

Consequently, the receive margin in asynchronous mode can be expressed as shown in equation
(1).
M ={(0.5 – 1 ) – D – 0.5
2N
where
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
M = {0.5 — 1/(2 × 16)} × 100 [%]
= 46.875%
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
Rev. 6.00 Aug 04, 2006 page 406 of 680
REJ09B0145-0600
16 clock pulses
8 clock pulses
7
Start bit
– (L – 0.5) F} × 100 [%]
N
..... Equation (2)
15 0 7
D0
..... Equation (1)
15 0
D1