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Section 15 Serial Communication Interface (SCI)
15.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse
of the basic clock, data is latched at the middle of each bit, as shown in figure 15.3. Thus the
reception margin in asynchronous mode is determined by formula (1) below.
M = (0.5 –
}
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 1.00 Apr. 28, 2008 Page 426 of 994
REJ09B0452-0100
1
D – 0.5
) –
(1 + F) – (L – 0.5) F } × 100
2N
N
16 clocks
8 clocks
0
7
Start bit
... Formula (1)
[%]
15 0
7
D0
15 0
D1
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