Data Read Extended Address Setting Register (Drear) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.6

Data Read Extended Address Setting Register (DREAR)

DREAR is a 32-bit register that sets the address when the serial flash address is output in 32-bit mode.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value:
0
R/W:
R
Bit Bit Name
31 to 24 ―
23 to 16 EAV[7:0]
15 to 3 ―
2 to 0 EAC[2:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
H'00 R/W
All 0 R
000 R/W
25 24 23 22 21
- -
0 0 0 0 0
R R R/W R/W R/W
9 8 7 6 5
- - - - -
0 0 0 0 0
R R R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
32-Bit Extended Upper Address Fixed Value
Sets the upper address bit values of the external address specified by the
EAC[2:0] bits when the serial flash address is output in 32-bit mode.
Bit 0 corresponds to the serial flash address bit [25], and bit 7
corresponds to the bit [32].
This setting is valid when the ADE[3] bit in DRENR is 1.
When EAC[2:0] are 000, serial flash address [32:25] fixed values should
be set to EAV[7:0].
When EAC[2:0] are 001, serial flash address [32:26] fixed values should
set to EAV[7:1].
(1) When BSZ[1:0] in CMNCR = 00 (one serial flash memory connected)
Serial flash addresses [31:0] are used for accessing.
(2) When BSZ[1:0] in CMNCR = 01 (two serial flash memories
connected)
Serial flash addresses [32:1] are used for accessing.
Reserved
These bits are always read as 0. The write value should always be 0.
32-Bit Extended External Address Valid Range
Sets the range of the external address to be used as serial flash address
when the serial flash address is output in 32-bit mode.
This setting is valid when the ADE[3] bit in DRENR is 1.
000: External address bits [24:0] enabled
001: External address bits [25:0] enabled
Other than above: Setting prohibited
17. SPI Multi I/O Bus Controller
20 19 18 17 16
EAV[7:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
- - EAC[2:0]
0 0 0 0 0
R R R/W R/W R/W
17-13