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FAULT DESCRIPTION
Configuration and control registers CRC fault
User EEPROM space CRC fault
Trim EEPROM space CRC fault
SPI communication fault
Analog BIST fault
Logic BIST fault
Oscillator fault
FAULT pin read-back missmatch error
Numerical overflow of tracking loop
Open circuit on ground pin fault
7.4 Device Functional Modes
The PGA411-Q1 device implements a digital state machine that is responsible for device functional operation,
decision making, and system monitoring.
the SPI is active the current device-operating state is found by reading the DEVSTATE bits in the DEV_STAT7
register.
~NRESET
|
Oscillator_Fault |
Thermal_Shutdown |
VDD Under_Voltage |
VCC Under_Voltage
(2)
RESET
FAULT = 0
Boost = OFF
Exciter = OFF
DTL = OFF
Symbol Legend:
~
Logical NOT
&
Logical AND
|
Logical OR
: SPI Value change
" Boost refers to the Exciter Power Supply (Boost Regulator).
" Exciter refers to the Exciter Signal Power Amplifier.
" DTL refers to the integrated Digital Tracking Loop.
(1) Depends on Exciter Override selection, behavior implementation, or both as listed in
(2) Not a physical state. When the device is in the RESET state, an nPOR signal is asserted to digital logic.
(3) Setting the EXTEN bit to 1 enables the exciter amplifier. Setting the LPEN bit to 1 enables the digital tracking loop.
7.4.1 PGA411-Q1 Reset
The RESET state is not a physical state-machine controller state. The RESET state in
nPOR asserted in the PGA411-Q1 device, forcing the digital logic into reset (digital is frozen). On nPOR release
the digital logic begins operating from the DIAGNOSTICS state.
In the system, the NRESET pin asserts the nPOR in the device logic. When the NRESET pin is low (DGND), the
PGA411-Q1 logic is frozen and the device is in the RESET state. When the NRESET pin is pulled up, the logic is
enabled after a 70-µs deglitch period and the device is operational.
Copyright © 2015–2017, Texas Instruments Incorporated
Table 4. PGA411-Q1 Fault Reporting Summary (continued)
SPI FAULT BIT
FRCRC
FCECRC
FTECRC
SPI_ERR
ABISTF
LBISTF
(RESET state)
IOFAULT
FLOOP_CLAMP
FGOPEN
Figure 2
DIAGNOSTICS
NRESET
FAULT = 0
Boost = OFF
(3)
Exciter = OFF
(3)
DTL = OFF
Internal Signal
Device Pin
Figure 38. State Diagram
Product Folder Links:
SLASE76E – NOVEMBER 2015 – REVISED AUGUST 2017
FAULT PIN MASK
BIT
shows a detailed timing diagram of device power up. When
[~ABISTF & ~LBISTF &
~FAFECAL] |
[63, : ',$*(;,7 = 1]
NORMAL
FAULT = 0
Boost = ON
Exciter = ON/OFF
DTL = ON
[63, : 63,',$* = 1]
fault_list:
[EXTMODE = 00 | EXTMODE = 11] |
[EXTOV & ~MEXTOV] |
[EXTUV & ~MEXTUV] |
[(FEXTMONH | FEXTMONL) & ~MEXTMON] |
[FIZHx & ~MIZOVx] |
[FIZLx & ~MIZUVx] |
[FOSHORT & ~MFOSHORT] |
[FOSINOPH & ~MFOSINOPH] |
[FOCOSOPH & ~MFOCOSOPH] |
[FOSINOPL & ~MFOSINOPL] |
[FOCOSOPL & ~MFOCOSOPL] |
[FLOOPE & ~ MFLOOPE] |
PGA411-Q1
PGA411-Q1
FAULT PIN
EXCITER
STATE
OUTPUT
OVERRIDE
Off
On
Hi-Z / High
(1)
Off
Low
Off
(1)
—
Off
ENIOFAULT
Low
On
Hi-Z / High
Off
fault_list
FAULT = Hi-Z/High
Boost = ON
(1)
Exciter = ON/OFF
DTL = OFF
FAULTRES
FBSTOV |
FVCCOV |
FVDDOV |
FVDDOC |
FTSD2 |
FGOPEN |
FRCRC |
FCECRC |
FTECRC |
SPI_ERR |
ABISTF |
LBISTF
Table
4.
Figure 38
signifies an
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EXCITER
ENBISTF
FAULT
(1)
45
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