Basic Operational Timing; Overview; On-Chip Memory Access Timing - Renesas H8/3067 Series User Manual

Section 2 CPU
2.9

Basic Operational Timing

2.9.1

Overview

The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the
system clock to the next rise is referred to as a "state." A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2

On-Chip Memory Access Timing

On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin
states.
φ
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
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T state
Figure 2.15 On-Chip Memory Access Cycle
Bus cycle
T state
1 2
Address
Read data
Write data