Timer Control Register (Tcr) - Renesas H8S/2100 Series Hardware Manual

Channel Register Name
Channel 2 Timer general register A_2
Timer general register B_2
Common Timer start register
Timer synchro register
10.3.1

Timer Control Register (TCR)

The TCR registers control the TCNT operation for each channel. The TPU has a total of three
TCR registers, one for each channel (channel 0 to 2). TCR register settings should be made only
when TCNT operation is stopped.
Bit Bit Name
7 CCLR2
6 CCLR1
5 CCLR0
4 CKEG1
3 CKEG0
2 TPSC2
1 TPSC1
0 TPSC0
[Legend]
x: Don't care
Initial
value R/W Description
0 R/W Counter Clear 2 to 0
0 R/W These bits select the TCNT counter clearing source.
For details, see tables 10.4 and 10.5.
0 R/W
0 R/W Clock Edge 1 and 0
0 R/W These bits select the input clock edge. When the input
clock is counted using both edges, the input clock cycle
is divided in 2 (φ/4 both edges = φ/2 rising edge). If
phase counting mode is used on channels 1, 2, 4, and
5, this setting is ignored and the phase counting mode
setting has priority. Internal clock edge selection is valid
when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1 and rising edge count is
selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
0 R/W Time Prescaler 2 to 0
0 R/W These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
0 R/W
For details, see tables 10.6 to 10.8.
Section 10 16-Bit Timer Pulse Unit (TPU)
Abbreviation R/W
TGRA_2 R/W
TGRB_2 R/W
TSTR R/W
TSYR R/W
Rev. 1.00 May 09, 2008 Page 229 of 954
Initial Data Bus
Value Address Width
H'FFFF H'FE78 16
H'FFFF H'FE7A 16
H'00 H'FEB0 8
H'00 H'FEB1 8
REJ09B0462-0100