Timer Control Register (Tcr) - Renesas H8SX/1520 Series Hardware Manual

9.3.1

Timer Control Register (TCR)

TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one
for each channel. TCR register settings should be made only while TCNT operation is stopped.
Bit
Bit Name
Initial Value
R/W
Bit Bit Name
7 CCLR2
6 CCLR1
5 CCLR0
4 CKEG1
3 CKEG0
2 TPSC2
1 TPSC1
0 TPSC0
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7 6
CCLR2 CCLR1 CCLR0
0 0
R/W R/W
Initial
Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
5 4
CKEG1 CKEG0
0 0
R/W R/W R/W
Description
Counter Clear 2 to 0
These bits select the TCNT counter clearing source. See
tables 9.5 and 9.6 for details.
Clock Edge 1 and 0
These bits select the input clock edge. For details, see
table 9.7. When the input clock is counted using both
edges, the input clock period is halved (e.g. Pφ/4 both
edges = Pφ/2 rising edge). If phase counting mode is
used on channels 1, 2, 4, and 5, this setting is ignored
and the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is Pφ/4
or slower. This setting is ignored if the input clock is Pφ/1,
or when overflow/underflow of another channel is
selected.
Timer Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 9.8 to 9.13 for details. To select the external
clock as the clock source, the DDR bit and ICR bit for the
corresponding pin should be set to 0 and 1, respectively.
For details, see section 8, I/O Ports.
Section 9 16-Bit Timer Pulse Unit (TPU)
3 2 1
TPSC2 TPSC1
0 0 0
R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 265 of 804
0
TPSC0
0
R/W
REJ09B0104-0300