Dtc Source Address Register (Sar); Dtc Destination Address Register (Dar); Dtc Transfer Count Register A (Cra); Dtc Transfer Count Register B (Crb) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

Hide thumbs Also See for H8S Series:

Table of Contents

DTC Source Address Register (SAR)

Initial value :

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer,

specify an even source address.

Initial value :

DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size

transfer, specify an even destination address.

Initial value :

← CRAH → ← CRAL →

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time

data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits

(CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is

decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This

operation is repeated.

Initial value :

Rev.6.00 Oct.28.2004 page 246 of 1016

REJ09B0138-0600H