Table 6.2 Bus Specifications For Each Area (Basic Bus Interface) - Renesas H8S/2368 Series Hardware Manual

Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR
ABWn ASTn
0 0
1
1 0
1
Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of
the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in
the basic bus interface space.
CS) Assertion Period Extension States: Some external I/O devices require a setup CS CS
Chip Select (CS
time and hold time between address and CS signals and strobe signals such as RD, HWR, and
LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle.
WTCRA, WTCRB
Wn2 Wn1 Wn0
— — —
0 0 0
1
1 0
1
1 0 0
1
1 0
1
— — —
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Bus Specifications (Basic Bus Interface)
Access
Bus Width States
16 2
3
8 2
3
Rev. 2.00, 05/03, page 135 of 820
Program Wait
States
0
0
1
2
3
4
5
6
7
0
0
1
2
3
4
5
6
7
(n = 0 to 7)