Basic Bus Interface; Overview; Data Size And Data Alignment - Renesas H8S Series Hardware Manual

6.4

Basic Bus Interface

6.4.1

Overview

The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3).
6.4.2

Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data
alignment function, and when accessing external space, controls whether the upper data bus (D
(D to D ) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space)
7 0
and the data size.
8-Bit Access Space: Figure 6-4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D to D
15
a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses.
Byte size
Word size
Longword size
Figure 6-4 Access Sizes and Data Alignment Control (8-Bit Access Space)
) is always used for accesses. The amount of data that can be accessed at one time is one byte:
8
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Upper data bus Lower data bus
D D D
15 8 7
Rev.6.00 Oct.28.2004 page 125 of 1016
to D ) or lower data bus
15 8
D
0
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