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M16C/29 Group
16. Multi-master I
2
The multi-master I
C bus interface is a serial communication circuit based on Philips I
format. 2 independent channels, with both arbitration lost detection and synchronous functions, are built in
for the multi-master serial communication. Figure 16.1 shows a block diagram of the multi-master I
interface and Table 16.1 lists the multi-master I
2
The multi-master I
C bus interface consists of the I
clock control register, the I
start/stop condition control register and other control circuits.
Figure 16.2 to 16.8 show the registers associated with the multi-master I
Table 16.1 Multi-master I
Item
Format
Communication mode
SCL clock frequency
2
Note 1. V
=I
C system clock
IIC
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
2
C bus Interface
2
C0 control register 1, I
2
C bus interface functions
Function
Based on Philips I
7-bit addressing format
High-speed clock mode
Standard clock mode
Based on Philips I
Master transmit
Master receive
Slave transmit
Slave receive
16.1kHz to 400kHz (at V
page 247 of 402
16. MULTI-MASTER I
2
C bus interface functions.
2
C0 address register, the I
2
C0 control register 2, the I
2
C bus standard:
2
C bus standard:
(Note 1)
IIC
2
C bus INTERFACE
2
C bus data transfer
2
C0 data shift register, the I
2
C0 status register, the I
2
C bus.
= 4MHz)
2
C bus
2
C0
2
C0
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