Table of Contents
Advertisement
1.7.4 SiP internal-connection bus interface pins
(1) Access timing (SRAM, external ROM, external I/O)
Table 1-15. Access Timing (SRAM, External ROM, External I/O)
Parameter
Address, SCSZ0-SCSZ3 output delay time (from SBUSCLK ↑ )
SRDZ, SIORDZ ↓ delay time (from SBUSCLK ↓ )
SRDZ, SIORDZ ↑ delay time (from SBUSCLK ↑ )
SWRZ0 to SWRZ1, SWRSTBZ, SIOWRZ ↓ (from SBUSCLK ↓ )
SWRZ0 to SWRZ1, SWRSTBZ, SIOWRZ ↑ ( from SBUSCLK ↓ )
SBCYSTZ ↓ delay time (from SBUSCLK ↑ )
SBCYSTZ ↑ delay time (from SBUSCLK ↑ )
SWAITZ setup time (to SBUSCLK ↑)
SWAITZ hold time (from SBUSCLK ↑ )
Data input setup time (to SBUSCLK ↑ )
Data input hold time (from SBUSCLK ↑ )
Data output delay time (from SBUSCLK ↑ )
Data float delay time (from SBUSCLK ↑ )
32
CHAPTER 1 PRODUCT SPECIFCATIONS
Symbol
t
DKA
t
DKRDL
t
DKRDH
t
DKWRL
t
DKWRH
t
DKBSL
t
DKBSH
t
SKW
t
HKW
t
SKID
t
HKID
t
DKOD
t
HKOD
User's Manual A19069EJ2V0UM
MIN.
MAX.
1.5
11.0
1.5
11.0
1.5
11.0
1.5
11.0
1.5
11.0
1.5
8.0
1.5
8.0
−
3.0
−
1.0
3.0
−
2.0
−
1.5
11.0
1.5
11.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Advertisement
Table of Contents
