Usage Notes; Contention Between Interrupt Generation And Disabling; Instructions That Disable Interrupts - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

Hide thumbs Also See for H8S Series:

Table of Contents

Usage Notes

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the

instruction.

In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is

generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction,

and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there

is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-

priority interrupt, and the lower-priority interrupt will be ignored.

The same also applies when an interrupt source flag is cleared.

Figure 5-8 shows an example in which the TGIEA bit in the TPU's TIER0 register is cleared to 0.

write signal

interrupt signal

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all

interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these

instructions, the new value becomes valid two states after execution of the instruction ends.

TIER0 write cycle by CPU

TIER0 address

Figure 5-8 Contention between Interrupt Generation and Disabling

TGI0A exception handling

Rev.6.00 Oct.28.2004 page 99 of 1016

REJ09B0138-0600H