Instructions That Disable Interrupts; When Interrupts Are Disabled; Figure 5.6 Contention Between Interrupt Generation And Disabling - Renesas H8S Series Hardware Manual

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
φ
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal

Figure 5.6 Contention between Interrupt Generation and Disabling

5.7.2

Instructions that Disable Interrupts

The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3

When Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
TIER_0 write cycle by CPU
TIER_0 address
Section 5 Interrupt Controller
TCIVexception handling
Rev. 6.00 Mar 15, 2006 page 87 of 570
REJ09B0211-0600