Address Break Control Register (Abrkcr); Table 5.2 Correspondence Between Interrupt Source And Icr - Renesas H8S/2111B Hardware Manual

Table 5.2 Correspondence between Interrupt Source and ICR
Bit Bit Name
7 ICRn7
6 ICRn6
5 ICRn5
4 ICRn4
3 ICRn3
2 ICRn2
1 ICRn1
0 ICRn0
[Legend]
n: A to C
:
Reserved. The write value should always be 0.
5.3.2

Address Break Control Register (ABRKCR)

ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit Bit Name
7 CMF
6 —
to
1
0 BIE
Rev. 1.00, 05/04, page 70 of 544
ICRA
IRQ0
IRQ1
IRQ2, IRQ3
IRQ4, IRQ5
IRQ6, IRQ7
—
WDT_0
WDT_1
Initial
Value R/W
0 R
All 0 R
0 R/W
Register
ICRB
—
FRT
—
—
TMR_0
TMR_1
TMR_X, TMR_Y
Keyboard buffer controller
Description
Condition Match Flag
Address break source flag. Indicates that an address
specified by BARA to BARC is prefetched.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE flag is set to 1.
[Clearing condition]
When an exception handling is executed for an
address break interrupt.
Reserved
These bits are always read as 0 and cannot be
modified.
Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
ICRC
—
SCI_1
—
IIC_0
IIC_1
TMR_A, TMR_B
LPC
—