Address Break Control Register (Abrkcr) - Renesas H8S/2100 Series Hardware Manual

5.3.2

Address Break Control Register (ABRKCR)

ABRKCR controls the address breaks. When both the CMF flag and BIE bit are set to 1, an
address break is requested.
Bit Bit Name Initial Value
7 CMF Undefined
6 to 1 — All 0
0 BIE 0
R/W Description
R Condition Match Flag
Address break source flag. Indicates that an address
specified by BARA to BARC is prefetched.
[Clearing condition]
When an exception handling is executed for an address
break interrupt.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE bit is set to 1.
R Reserved
These bits are always read as 0 and cannot be modified.
R/W Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
Section 5 Interrupt Controller
Rev. 1.00 Apr. 28, 2008 Page 91 of 994
REJ09B0452-0100