Address Break Control Register (Abrkcr) - Renesas H8S/2158 User Manual

5.3.2

Address Break Control Register (ABRKCR)

ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit Bit Name
7 CMIF
6 —
to
1
0 BIE
Initial Value R/W
Undefined R/W
All 0 R
0 R/W
Section 5 Interrupt Controller
Description
Condition Match Flag
Address break source flag. Indicates that an
address specified by BARA to BARC is
prefetched.
[Clearing condition]
When an exception handling is executed for an
address break interrupt.
[Setting condition]
When an address specified by BARA to BARC
is prefetched while the BIE flag is set to 1.
Reserved
These bits are always read as 0 and cannot be
modified.
Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
Rev. 3.00 Jan 25, 2006 page 77 of 872
REJ09B0286-0300