Interrupts After Reset; State Of On-Chip Supporting Modules After Reset Release; Traces - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved

correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after

a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that

this instruction initializes the stack pointer (example: MOV.L #xx:32, SP).

After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC and DTC enter module stop

mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is

enabled when module stop mode is exited.

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the

state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each

instruction.

Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.

Table 4-4 shows the state of CCR and EXR after execution of trace exception handling.

Interrupts are accepted even within the trace exception handling routine.

The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine

by the RTE instruction, trace mode resumes.

Trace exception handling is not carried out after execution of the RTE instruction.

Status of CCR and EXR after Trace Exception Handling

Interrupt Control Mode

0: Cleared to 0

—: Retains value prior to execution.

Rev.6.00 Oct.28.2004 page 76 of 1016

REJ09B0138-0600H

Trace exception handling cannot be used.