Interrupts After Reset; State Of On-Chip Supporting Modules After Reset Release; Figure 4.2 Reset Sequence - Renesas H8S Series Hardware Manual

φ
RES
Address bus
RD
HWR, LWR
D15 to D0
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note: * Three program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled: Cannot be Used
4.3.2

Interrupts after Reset

If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3

State of On-Chip Supporting Modules after Reset Release

After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively,
and all modules except the DTC enter module stop mode. Consequently, on-chip supporting
Vector fetch
* *
(1) (3)
High
(2)
in this LSI)
Rev. 6.00 Mar 15, 2006 page 61 of 570
Section 4 Exception Handling
Internal Prefetch of first
processing program instruction
*
(5)
(4) (6)
REJ09B0211-0600