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Section 5 Exception Handling
Figure 5.1 shows an example of the reset sequence.
φ
RES
Power-on internal
reset signal
Internal address bus
Internal read signal
Internal write signal
Internal data bus
(1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2)U + (2)L)
(4) First program instruction
5.3.2
Interrupts Immediately after Reset
If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized,
the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all
interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction
of a program is always executed immediately after a reset, make sure that this instruction
initializes the SP (example: MOV.L #xx: 32, SP).
5.3.3
On-Chip Peripheral Modules after Reset is Cancelled
After a reset is cancelled, the module stop control registers (MSTPCRH, MSTPCRL, MSTPCRA,
MSTPCRB) are initialized, and all modules except the DTC operate in module stop mode.
Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read
from and write to these registers, clear module stop mode. For details on module stop mode, see
section 26, Power-Down Modes.
Rev. 1.00 May 09, 2008 Page 92 of 954
REJ09B0462-0100
Figure 5.1 Reset Sequence (Mode 2)
Vector
Internal
fetch
processing
(1) U
(1) L
High
(2)
(2)
U
L
Prefetch of first
program instruction
(3)
(4)
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