Serial Status Register (Ssr) - Renesas H8 Series Hardware Manual

Section 10 Serial Communication Interface
10.2.7

Serial Status Register (SSR)

Bit 7
TDRE
Initial value 1
R/(W) *
Read/Write
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written to by the CPU at any time, but 1 cannot be written to bits TDRE,
RDRF, OER, PER, and FER.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.
Bit 7—Transmit Data Register Empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE Description
0 Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1 Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
Rev. 7.00 Mar 10, 2005 page 344 of 652
REJ09B0042-0700
6 5
RDRF OER FER
0 0
R/(W) * R/(W) * R/(W) *
4 3 2
PER TEND
0 0 1
R/(W) *
R
1 0
MPBR MPBT
0 0
R R/W
(initial value)