Serial Status Register (Ssr) - Renesas H8S/2100 Series Hardware Manual

Section 15 Serial Communication Interface (SCI)
15.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit Bit Name
7 TDRE
6 RDRF
5 ORER
Rev. 1.00 Apr. 28, 2008 Page 414 of 994
REJ09B0452-0100
Initial Value R/W
1 R/(W)* Transmit Data Register Empty
0 R/(W)* Receive Data Register Full
0 R/(W)* Overrun Error
Description
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and
TDR is ready for data write
[Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
Indicates that receive data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing condition]
When 0 is written to RDRF after reading RDRF = 1
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0.
[Setting condition]
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
When 0 is written to ORER after reading ORER = 1