Serial Status Register (Ssr) - Renesas H8SX/1520 Series Hardware Manual

Bit Bit Name
1 CKE1
0 CKE0
12.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• When SMIF in SCMR = 0
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written, to clear the flag.
• When SMIF in SCMR = 1
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written, to clear the flag.
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Initial
Value R/W
0 R/W
0 R/W
7 6
TDRE RDRF ORER
1 0
R/(W)* R/(W)* R/(W)*
7 6
TDRE RDRF ORER
1 0
R/(W)* R/(W)* R/(W)*
Section 12 Serial Communication Interface (SCI)
Description
Clock Enable 1, 0
These bits control the clock output from the SCK pin. In
GSM mode, clock output can be dynamically switched.
For details, see section 12.7.8, Clock Output Control.
•
When GM in SMR = 0
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1X: Reserved
•
When GM in SMR = 1
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
5 4 3
FER PER
0 0 0
R/(W)* R/(W)*
5 4 3
ERS PER
0 0 0
R/(W)* R/(W)*
2 1
TEND MPB
1 0
R R
2 1
TEND MPB
1 0
R R
Rev. 3.00 Mar. 14, 2006 Page 389 of 804
REJ09B0104-0300
0
MPBT
0
R/W
0
MPBT
0
R/W