Serial Status Register (Ssr) - Renesas H8SX/1500 Series Hardware Manual

Bit Bit Name
1 CKE1
0 CKE0
12.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• When SMIF in SCMR = 0
Bit 7
Bit Name TDRE
1
Initial Value
R/W R/(W)*
Note: * Only 0 can be written, to clear the flag.
• When SMIF in SCMR = 1
Bit 7
Bit Name TDRE
Initial Value 1
R/W R/(W)*
Note: * Only 0 can be written, to clear the flag.
Initial
Value R/W Description
0 R/W Clock Enable 1, 0
0 R/W These bits control the clock output from the SCK pin. In
GSM mode, clock output can be dynamically switched.
For details, see section 12.7.8, Clock Output Control.
•
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1X: Reserved
•
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
6 5
RDRF ORER
0 0
R/(W)* R/(W)*
6 5
RDRF ORER
0 0
R/(W)* R/(W)*
Section 12 Serial Communication Interface (SCI)
When GM in SMR = 0
When GM in SMR = 1
4 3
FER PER
0 0
R/(W)* R/(W)*
4 3
ERS PER
0 0
R/(W)* R/(W)*
Rev. 3.00 Mar. 14, 2006 Page 389 of 804
2 1
TEND MPB
1 0
R R
2 1
TEND MPB
1 0
R R
REJ09B0104-0300
0
MPBT
0
R/W
0
MPBT
0
R/W