Bus Transfer Timing - Renesas H8S/2158 User Manual

6.9.2

Bus Transfer Timing

When a bus request is received from a bus master with a higher priority than that of the bus master
that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. Each bus master can relinquish the bus at the timings given below.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or
RFU, the bus arbiter transfers the bus to the DTC.
• DTC bus transfer timing
 The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred
between the component operations. For details, refer to section 2.7, Bus States During
Instruction Execution in the H8S/2600 Series, H8S/2000 Series Programming Manual.
 If the CPU is in sleep mode, the bus is transferred immediately.
• RFU bus transfer timing
 The bus is transferred at a break between bus cycles. Even in discrete operations, as in the
case of a longword-size access, the bus can be transferred between the component
operations. For details, refer to section 8, RAM-FIFO Unit (RFU).
 If the CPU is in sleep mode, the bus is transferred immediately.
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
Since the bus master priority of the DTC is lower than the RFU, the bus arbiter transfers the bus
mastership from the DTC to the RFU if the RFU requests the bus.
• RFU bus transfer timing
The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations. In addition, in 32-bit access by the DTC, the bus is not transferred
at a break between longword access cycles. For details, refer to section 8, RAM-FIFO Unit
(RFU).
RFU: The RFU has the highest bus master priority. The RFU sends the bus arbiter a request for
the bus when an activation request is generated. The RFU does not release the bus until it
completes its operation. For details, refer to section 8, RAM-FIFO Unit (RFU).
Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 143 of 872
REJ09B0286-0300